 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MOS INTEGRATED CIRCUIT PD75312B, 75316B 4-BIT SINGLE-CHIP MICROCOMPUTER The PD75316B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an 8bit microcomputer. It is a low-voltage operation version of the PD75316 with an on-chip LCD controller/driver. Operation at an ultralow voltage of 2.0 V is possible. An ultra small-sized plastic TQFP (12 x 12 mm) is also provided and it is suitable for small-sized sets that use an LCD panel. A detailed explanation of the functions will be given in the user's manual listed below. It should be read before starting design work. PD75308 User's Manual: IEM-1263 FEATURES * Ultra-low-voltage operation possible: VDD = 2.0 to 6.0 V * Instruction execution time adjustment function * Can be driven by two 1.5-V manganese batteries. * On-chip memory * Program memory (ROM) : 16256 x 8 bits (PD75316B) : 12160 x 8 bits (PD75312B) * Data memory (RAM) : 1024 x 4 bits convenient in high-speed operation and power saving * 0.95 s, 1.91 s, 15.3 s (@ 4.19 MHz) * 122 s (@ 32.768 kHz) * On-chip programmable LCD controller/driver * LCD drive voltage: 2.0 V to VDD * Ultra small-sized plastic TQFP (12 x 12 mm) * Suitable for small-sized set, such as a camera. * PROM version PD75P316B also available. APPLICATIONS Remote control, camcorder, camera, gas meter, etc. ORDERING INFORMATION Part number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) PD75312BGC-xxx-3B9 PD75312BGK-xxx-BE9 PD75316BGC-xxx-3B9 PD75316BGK-xxx-BE9 Remark xxx: ROM code suffix Unless stated otherwise, the explanations in this document will use the PD75316B as a representative part. The information in this document is subject to change without notice. Document No. IC-3196A (O. D. No. IC-8698A) Date Published December 1994 P Printed in Japan (c) NEC Corporation 1993 PD75312B, 75316B FUNCTION OUTLINE (1/2) Item Number of basic instructions 41 Function Instruction cycle 0.95 s, 1.91 s, 15.3 s (main system clock: @ 4.19 MHz) 122 s (subsystem clock: @ 32.768 kHz) ROM 16256 x 8 bits (PD75316B), 12160 x 8 bits (PD75312B) 1024 x 4 bits * 4-bit access: 8 (B, C, D, E, H, L, X, A) * 8-bit access: 4 (BC, DE, HL, XA) * Bit accumulator (CY) * 4-bit accumulator (A) * 8-bit accumulator (XA) * * * * Various bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data transfer instructions GETI instruction that can implement 2-byte/3-byte instructions with 1 byte On-chip memory RAM General register Accumulators Instruction set 8 16 40 I/O lines 8 CMOS input with software-specifiable pull-up resistors : 23 CMOS input/output CMOS output N-ch open-drain input/output Used with segment pins 10-V withstand voltage, with mask option pullup resistors: 8 8 LCD controller/driver * Number of segments selection: 24/28/32 segments (4/8 can be switched at bit port output.) * Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty * LCD drive split resistor can be incorporated by mask option VDD = 2.0 to 6.0 V * 8-bit timer/event counter * Clock source: 4 stages * Event count possible Supply voltage range Timer 3 channels * 8-bit basic interval timer * Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (@ 4.19 MHz) * Watchdog timer application possible 2 PD75312B, 75316B FUNCTION OUTLINE (2/2) Item Function * Clock timer * 0.5-second time interval generation * Count clock source: Main system clock and subsystem clock switchable * Clock fast count mode (3.9-ms time interval generation) * Buzzer output possible (2 kHz) Timer 3 channels 8-bit serial interface * Three modes application possible * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode * LSB first/MSB first switchable Special bit manipulation memory: 16 bits * Perfect for remote control application Timer/event counter output (PTO0): square-wave output frequency specifiable Bit sequential buffer Clock output function Clock output (PCL): , 524, 262, 65.5 kHz (@ 4.19 MHz) Buzzer output (BUZ): 2 kHz (@ 4.19 MHz or 32.768 kHz) * External : 3 * Internal : 3 * External : 1 * Internal : 1 * Ceramic or crystal oscillator for main system clock oscillation: 4.194304 MHz * Crystal oscillator for subsystem clock oscillation: 32.768 kHz STOP/HALT mode * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) Vectored interrupt Test input System clock oscillator Standby Package 3 PD75312B, 75316B CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ........................................................................................................... 5 2. BLOCK DIAGRAM ........................................................................................................................................ 6 3. PIN FUNCTIONS .......................................................................................................................................... 7 3.1 3.2 3.3 3.4 PORT PINS .............................................................................................................................................................. 7 NON-PORT PINS .................................................................................................................................................... 9 PIN INPUT/OUTPUT CIRCUITS .......................................................................................................................... 10 RECOMMENDED CONNECTION OF UNUSED PINS ....................................................................................... 12 4. MEMORY CONFIGURATION .................................................................................................................... 13 5. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................................17 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS ................................................................................................................................................................... 17 CLOCK GENERATOR ........................................................................................................................................... 18 CLOCK OUTPUT CIRCUIT ................................................................................................................................... 19 BASIC INTERVAL TIMER .................................................................................................................................... 20 WATCH TIMER ..................................................................................................................................................... 21 TIMER/EVENT COUNTER ................................................................................................................................... 22 SERIAL INTERFACE ............................................................................................................................................. 24 LCD CONTROLLER/DRIVER ............................................................................................................................... 26 BIT SEQUENTIAL BUFFER ..... 16 BITS .............................................................................................................. 28 6. INTERRUPT FUNCTION ............................................................................................................................ 29 7. STANDBY FUNCTION ............................................................................................................................... 31 8. RESET FUNCTION ..................................................................................................................................... 32 9. INSTRUCTION SET .................................................................................................................................... 35 10. MASK OPTION SELECTION ..................................................................................................................... 42 11. ELECTRICAL SPECIFICATIONS ................................................................................................................ 43 12. CHARACTERISTIC CURVES (For Reference Only)................................................................................ 65 13. PACKAGE DRAWINGS .............................................................................................................................. 69 14. RECOMMENDED SOLDERING CONDITION .......................................................................................... 71 APPENDIX A. DIFFERENCES AMONG PD75308B SERIES PRODUCTS ................................................. 73 APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 74 APPENDIX C. RELATED DOCUMENTATION ...............................................................................................75 4 PD75312B, 75316B 1. PIN CONFIGURATION (TOP VIEW) S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 S11 S10 S9 S8 S7 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 2 59 3 58 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 S6 S5 S4 S3 S2 P60/KR0 X2 X1 IC* XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS * IC (Internally Connected) pin should be directly connected to VDD. P00 to 03 P10 to 13 P20 to 23 P30 to 33 P40 to 43 P50 to 53 P60 to 63 P70 to 73 BP0 to 7 KR0 to 7 SCK SI SO SB0,1 RESET : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Bit Port Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input S0 to 31 COM0 to 3 VLC0-2 BIAS LCDCL SYNC TI0 PTO0 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 IC P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 PD75312BGC-xxx-3B9 PD75312BGK-xxx-BE9 PD75316BGC-xxx-3B9 PD75316BGK-xxx-BE9 COM0 COM1 COM2 : : : : : : : : : : : : : : : Segment Output 0 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Internally Connected 5 6 BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 WATCH TIMER PROGRAM MEMORY (ROM) 16256 x 8 BITS : PD75316B 12160 x 8 BITS : PD75312B GENERAL REG. PROGRAM COUNTER (14) ALU CY PORT 2 BANK PORT 3 4 4 P20-P23 SP(8) PORT 0 PORT 1 4 4 P00-P03 P10-P13 P30-P33 BUZ/P23 PORT 4 4 4 P40-P43 INTW f LCD PORT 5 PORT 6 DATA MEMORY (RAM) 1024 x 4 BITS PORT 7 P50-P53 P60-P63 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73 BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL CLOCK DIVIDER INTERRUPT CONTROL fX / 2 N 2. BLOCK DIAGRAM DECODE AND CONTROL 4 4 P70-P73 24 S0-S23 S24/BP0 -S31/BP7 COM0-COM3 8 LCD CONTROLLER /DRIVER STAND BY CONTROL CPU CLOCK fLCD 4 PD75312B, 75316B SYSTEM CLOCK GENERATOR SUB MAIN 3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31 PCL/P22 XT1 XT2 X1 X2 VDD VSS RESET PD75312B, 75316B 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name P00 P01 P02 P03 P10 P11 Input/Output Input Input/output Input/output Input/output DualFunction Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 Function 8-bit I/O Reset I/O Circuit Type *1 B 4-bit input port (PORT 0) On-chip pull-up resistor can be specified for P01 to P03 as a 3-bit unit by software. F -A x Input F -B M-C With noise elimination function Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 -- -- PCL BUZ LCDCL SYNC INT2 TI0 PTO0 -- 4-bit input port (PORT 1) On-chip pull-up resistor can be specified as a 4-bit unit by software. x Input B -C 4-bit input/output port (PORT 2) On-chip pull-up resistor can be specified as a 4-bit unit by software. x Input E-B Programmable 4-bit input/output port (PORT 3) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software. x Input E-B P40 to P43 *2 Input/output -- N-ch open-drain 4-bit input/output port (PORT 4) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10-V withstand voltage N-ch open-drain 4-bit input/output port (PORT 5) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10-V withstand voltage High level (onchip pull-up resistor) or highimpedance M P50 to P53 *2 Input/output -- High level (onchip pull-up resistor) or highimpedance M * 1. : Schmitt triggered input 2. LED direct drive possible 7 PD75312B, 75316B 3.1 PORT PINS (2/2) Pin Name P60 P61 Input/Output DualFunction Pin KR0 KR1 Function 8-bit I/O Reset I/O Circuit Type *1 Input/output P62 P63 P70 P71 Input/output P72 P73 BP0 BP1 Output BP2 BP3 BP4 BP5 Output BP6 BP7 S30 S31 S26 S27 S28 S29 KR6 KR7 S24 S25 KR2 KR3 KR4 KR5 Programmable 4-bit input/output port (PORT 6) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software. Input F -A 4-bit input/output port (PORT 7) On-chip pull-up resistor can be specified as a 4-bit unit by software. Input F -A 1-bit output port (BIT PORT) Also used as segment output pin. x *2 G-C * 1. : Schmitt triggered input 2. BP0 to BP7 select VLC1 as the input source. However, the output level depends on BP0 to BP7 and VLC1 external circuit. BP0 to BP7 are connected mutually within the PD75316B. Therefore, the output level of BP0 to BP7 is determined by the value of R1, R2 and R3. Example PD75316B VDD R2 BP0 ON VLC1 R1 ON BP1 R3 8 PD75312B, 75316B 3.2 NON-PORT PINS Pin Name TI0 PTO0 PCL BUZ SCK SO/SB0 Input/Output Input Input/output Input/output Input/output Input/output Input/output DualFunction Pin P13 P20 P22 P23 P01 P02 Function External event pulse input pin to timer/event counter Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) Edge detection vectored interrupt input pin (detection edge selectable) Edge detection testable input pin (rising edge detection) Clocked Reset Input Input Input Input Input Input I/O Circuit Type *1 B -C E-B E-B E-B F -A F -B SI/SB1 Input/output P03 Input M -C INT4 INT0 INT1 INT2 KR0 to KR3 KR4 to KR7 S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL *4 SYNC *4 Input P00 P10 Input B Input P11 Input Input/output Input/output Output Output Output -- Output Input/output Input/output P12 P60 to P63 P70 to P73 -- BP0 to BP7 -- -- -- P30 P31 Input Asynchronous Asynchronous Input Input Input *2 *2 *2 -- *3 Input Input B -C B -C F -A F -A G-A G-C G-B -- -- E-B E-B Parallel falling edge detection testable input pin Parallel falling edge detection testable input pin Segment signal output pin Segment signal output pin Common signal output pin LCD drive power supply pin On-chip split resistor (mask option) External split resistor cut output pin External expansion driver drive clock output pin External expansion driver synchronization clock output pin Main system clock oscillation crystal/ceramic connection pin. For external clock, the external clock signal is input to X1 and the inverted phase is input to X2. Subsystem clock oscillation crystal connection pin. For external clock, the external clock signal is input to XT1 and XT2 is opened. XT1 can be used as a 1-bit input (test) pin. System reset input pin Internally Connected. Directly connected to VDD. Positive power supply pin GND potential pin X1, X2 Input -- -- -- XT1 XT2 RESET IC VDD VSS Input -- Input -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- * 1. : Schmitt triggered input * 2. Display outputs are selected with VLCX shown below as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, the level of each display output depends on the display output and VLCX external circuit. * 3. On-chip split resistor.........Low level No on-chip split resistor... High-impedance * 4. Pins provided for system expansion. Currently, only used as P30 and P31 pins. 9 PD75312B, 75316B 3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75316B are shown in schematic form. TYPE A (For TYPE E-B) TYPE D (For TYPE E-B, F-A) VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT Push-pull output that can be made high-impedance output CMOS Standard Input Buffer TYPE B (P-ch and N-ch OFF) TYPE E-B VDD P.U.R. P.U.R. enable IN P-ch data Type D output disable IN/OUT Type A P.U.R.:Pull-Up Resistor Schmitt-Triggered Input with Hysteresis Characteristic TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable data Type D output disable P.U.R. P-ch P-ch IN/OUT IN Type B P.U.R. : Pull-Up Resistor P.U.R.:Pull-Up Resistor 10 PD75312B, 75316B TYPE F-B VDD P.U.R. P.U.R. enable P-ch VDD P-ch TYPE G-C VDD P-ch VLC0 VLC1 P-ch SEG data/Bit Port data VLC2 N-ch OUT N-ch output disable (P) data output disable output disable (N) IN/OUT N-ch P.U.R.:Pull-Up Resistor TYPE G-A TYPE M VDD P.U.R. enable (Mask Option) IN/OUT VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.U.R.:Pull-Up Resistor output disable data N-ch OUT TYPE G-B TYPE M-C VDD VLC0 VLC1 P-ch P.U.R. enable P.U.R. P-ch IN/OUT P-ch N-ch OUT COM data N-ch VLC2 N-ch P-ch data output disable N-ch P.U.R.:Pull-Up Resistor 11 PD75312B, 75316B 3.4 RECOMMENDED CONNECTION OF UNUSED PINS Table 3-1 List of Recommended Connection of Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 to P12/INT2 Connect to VSS. P13/T10 P20/TO0 P21 P22/PCL P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40 to P43 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 S0 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS Connect to VSS. Connect to VSS when VLC0 to VLC2 unused. Otherwise leave open. XT1 XT2 IC Connect to VSS or VDD. Leave open. Directly connect to VDD. Leave open. Input state : Connect to VSS or VDD. Connect to VSS or VDD. Connect to VSS. Recommended Connection Output state : Leave open. 12 PD75312B, 75316B 4. MEMORY CONFIGURATION * Program memory (ROM) ... 16256 x 8 bits (0000H to 3F7FH) : PD75316B ... 12160 x 8 bits (0000H to 2F7FH) : PD75312B * 0000H to 0001H : Vector table in which program start address by reset is written. * 0002H to 000BH : Vector table in which program start address by interrupt is written. * 0020H to 007FH : Table area that is referred by GETI instruction. * Data Memory * Data area ... 1024 x 4 bits (000H to 3FFH) * Peripheral hardware area ... 128 x 4 bits (F80H to FFFH) 13 PD75312B, 75316B Fig. 4-1 Program Memory Map (a) PD75316B Address 7 0000H MBE 6 0 5 0 Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 INTBT/INT4 Start Address (High-Order 6 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 INT0 Start Address (High-Order 6 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 INT1 Start Address (High-Order 6 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 INTCSI Start Address (High-Order 6 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address BR !addr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address 0020H GETI Instruction Reference Table 007FH 0080H BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) 07FFH 0800H BRCB !caddr Instruction Branch Address Branch Destination Address and Subroutine Entry Address by GETI Instruction 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H BRCB !caddr Instruction Branch Address 3F7FH BRCB !caddr Instruction Branch Address 14 PD75312B, 75316B (b) PD75312B Address 7 0000H MBE 6 0 5 0 Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 INTBT/INT4 Start Address (High-Order 6 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 INT0 Start Address (High-Order 6 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 INT1 Start Address (High-Order 6 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 INTCSI Start Address (High-Order 6 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address BR !addr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address 0020H GETI Instruction Reference Table 007FH 0080H BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) 07FFH 0800H Branch Destination Address and Subroutine Entry Address by GETI Instruction 0FFFH 1000H 1FFFH 2000H BRCB !caddr Instruction Branch Address 2F7FH BRCB !caddr Instruction Branch Address 15 PD75312B, 75316B Fig. 4-2 Data Memory Map Data Memory 000H General Register Area 007H 008H Stack Area 256 x 4 (248 x 4) 0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display Data Memory Area 1FFH 200H (32 x 4) (8 x 4) Memory Bank 0 1 Data Area Static RAM (1024 x 4) 256 x 4 2 2FFH 300H 256 x 4 3 3FFH Not On-Chip F80H Peripheral Hardware Area 128 x 4 15 FFFH 16 PD75312B, 75316B 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O Ports has 4 types * * * * CMOS input (PORT0, 1) :8 CMOS input/output (PORT2, 3, 6, 7) : 16 N-ch open-drain (PORT4, 5) :8 CMOS output (BP0 to BP7) :8 Total 40 Table 5-1 Port Function Port (Symbol) Function Operation/Features This port can be used for reading or testing regardless of the operating mode of the dualfunction pin. Remarks Dual-function as pins INT4, SCK, SO/B0, SI/B1. Dual-function as pins INT0 to INT2 and TI0. Dual-function as pins LCDCL and SYNC. PORT0 4-bit input PORT1 PORT3* Can be set to 1-bit input or output mode. PORT6 PORT2 PORT7 PORT4* PORT5* 4-bit input/output (N-ch open-drain, 10-V withstand voltage) 4-bit input/output Can be set to 4-bit input or output mode. Ports 6 and 7 can be paired for 8-bit data input or output. Dual-function as pins KR0 to KR3. Dual-function as pins PTO0, PCL, BUZ. Dual-function as pins KR4 to KR7. Can be set to 4-bit input or output mode. Ports On-chip pull-up resistor specifiable bit4 and 5 can be paired for 8-bit data input or wise by mask oftion. output. BP0 to BP7 1-bit output Data output in 1-bit units. It is possible to switch The drive capability is small. For the output drive segment output S24 to S31 CMOS load drive. using the software. * LED can be driven directly. 17 PD75312B, 75316B 5.2 CLOCK GENERATOR The operation of the clock generator circuit is determined by the processor clock control register (PCC) and the system clock control register (SCC). There are two kinds of clocks; the main system clock and the subsystem clock. It is also possible to change the instruction execution time. * 0.95 s/1.91 s/15.3 s (main system clock: @ 4.19 MHz) * 122 s (sub-system clock: @ 32.768 kHz) Fig. 5-1 Clock Generator Block Diagram * Basic Interval Timer (BT) * Timer/Event Counter * Serial Interface * Watch Timer * LCD Controller/Driver * INT0 Noise Eliminator * Clock Output Circuit XT1 VDD XT2 X1 VDD X2 Main System Clock Oscillator fX 1/2 1/16 1/8 to 1/4096 Frequency Divider Subsystem Clock Oscillator fXT LCD Controller/ Driver Watch Timer WM. 3 SCC SCC3 Oscillation Stop Selector Selector Frequency Divider 1/4 * CPU * INT0 Noise Eliminator * Clock Output Circuit Internal Bus SCC0 PCC PCC0 PCC1 4 HALT * STOP * PCC2, PCC3 Clear PCC2 PCC3 R HALT F/F S Q STOP F/F Q S Wait Release Signal from BT RESET Signal R Standby Release Signal from Interrupt Control Circuit fX: fXT: : PCC: SCC: Main system clock frequency Subsystem clock frequency CPU clock Processor clock control register System clock control register 1. 2. * indicates instruction execution. one clock cycle (tCY) is one machine cycle instruction. For tCY, refer to AC characteristics in "11 ELECTRICAL SPECIFICATIONS." Remarks 18 PD75312B, 75316B 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit is used for outputting the clock pulse from the P22/PCL pins. It is used, for example, when a clock pulse is to be output to the remote control output, peripheral LSI, etc.. * Clock output (PCL) : , 524, 262, 65.5 kHz (4.19 MHz operation) The configuration of the clock output circuit is shown below. Fig. 5-2 Clock Output Circuit Configuration From Clock Generator fX/2 fX/2 fX/2 3 Output Buffer Selector PCL/P22 4 6 PORT2.2 CLOM3 0 CLOM1CLOM0 CLOM P22 Output Latch Bit 2 of PMGB Bit Specified In Port 2 Input/Output Mode 4 Internal Bus Remark Consideration is given so that a low-amplitude pulse is not output when switching between clocks. 19 PD75312B, 75316B 5.4 BASIC INTERVAL TIMER The basic interval timer includes the following functions. * It operates as an interval timer which generates reference time interrupts. * It can be applied as a watchdog timer which detects inadvertent program loop. * Selects and counts wait times when the standby mode is released. * It reads count contents. Fig. 5-3 Basic Interval Timer Configuration From Clock Generator fX/2 5 Clear Clear fX/2 7 MPX fX/2 fX/2 9 Basic Interval Timer (8-Bit Frequency Divider) Set BT Interrupt Request Flag 12 BT IRQBT Vectored Interrupt Request Signal 3 Wait Release Signal during Standby Release BTM3 BTM2 BTM1 BTM0 BTM *SET1 4 Internal Bus 8 Remark * indicates instruction execution. 20 PD75312B, 75316B 5.5 WATCH TIMER The PD75316B incorporates a watch timer channel. The watch timer has the following functions. * Sets test flags (IRQW) at 0.5-second intervals. The standby mode can be released with IRQW. * 0.5-second time intervals can be created in either the main system clock or the subsystem clock. * In the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. * A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and trimming system clock oscillator frequencies. * The frequency divider can be cleared, enabling creation of watches that can start from 0 second. Fig. 5-4 Watch Timer Block Diagram fW 6 2 (512 Hz : 1.95 ms) fLCD fW (256 Hz : 3.91 ms) 7 2 fX 128 (32.768 kHz) fXT (32.768 kHz) Selector INTW IRQW Set Signal From Clock Generator Selector fW (32.768 kHz) fW 14 2 Frequency Divider 2Hz 0.5 sec fW 16 (2.048 kHz) Clear Output Buffer P23/BUZ WM WM7 0 0 0 WM3 WM2 WM1 WM0 PORT2.3 P23 Output Latch Bit 2 of PMGB Port 2 Input/Output Mode 8 Bit Test Instruction Internal Bus Remark Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz. 21 PD75312B, 75316B 5.6 TIMER/EVENT COUNTER The PD75316B incorporates a timer/event counter channel. The functions of the timer/event counter are as follows. * * * * * * Operates as a programmable interval timer. Outputs square waves in the desired frequency to the PTO0 pin. Operates as an event counter. Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation). Supplies a serial shift clock to the serial interface circuit. Count status read function. 22 Fig. 5-5 Timer/Event Counter Block Diagram Internal Bus SET1 8 TM06 TM05 TM04 TM03 TM02 *1 TM0 8 8 Modulo Register (8) TMOD0 TOE0 TO Enable Flag PORT2.0 Bit 2 of PGMB Port 2 P20 Input/ Output Output Latch Mode To Serial Interface P20/PTO0 Output Buffer INTT0 IRQT0 Set Signal PORT1.3 8 Comparator (8) Match TOUT F/F Reset T0 Input Buffer P13/TI0 *2 From Clock Generator MPX 8 Count Register (8) CP Clear Timer Operation Start RESET IRQT0 Clear Signal PD75312B, 75316B * 1. SET1: Instruction execution 2. For detail, see Fig. 5-1. 23 PD75312B, 75316B 5.7 SERIAL INTERFACE The PD75316B incorporates a clocked 8-bit serial interface which has the following three types of mode. * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode (serial bus interface mode) 24 Fig. 5-6 Serial Interface Block Diagram Internal Bus 8/4 Bit Test CSIM 8 8 8 Slave Address Register (SVA) Bit Manipulation (8) Match Signal (8) RELT CMDT SBIC Bit Test Addres Comparator P03/SI/SB1 Selector Shift Register (SIO) (8) SO SET CLR Latch D Q P02/SO/SB0 Selector Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detector RELD CMDD ACKD P01/SCK ACKT ACKE BSYE Serial Clock Counter P01 Output Latch INTCSI Control Circuit IRQCSI set signal INTCSI Serial Clock Control Circuit Serial Clock Slector fX/24 fX/2 6 fX/2 TOUT F/F (From Timer/ Event Counter) External SCK 3 PD75312B, 75316B 25 PD75312B, 75316B 5.8 LCD CONTROLLER/DRIVER The PD75316B has an on-chip display controller which generates segment signals and common signals in accordance with data in display data memory as well as a segment driver and common driver capable of directly driving the LCD panel. The configuration of the LCD controller/driver is shown in Fig. 5-7. The functions of the LCD controller/driver are as follows. * Display data memory are read automatically through DMA operations and segment signals and common signals are generated. * 5 different display modes can be selected. 1 Static 2 1/2 duty (1/2 bias) 3 1/3 duty 4 1/3 duty 5 1/4 duty * In each of COM3). (1/2 bias) (1/3 bias) (1/3 bias) the display modes, 4 types of frame frequency can be selected. * The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to * Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use as output ports (BP0 to BP3, BP4 to BP7). * Split resistors can be incorporated for the LCD drive power supply (mask option). Conformity to various bias methods and LCD drive voltages is possible. * When the display is OFF, the current flowing to the split resistors is cut. * Display data memory not used for the display can be used as ordinary data memory. * * Operation by the subsystem clock is also possible. 26 Fig. 5-7 LCD Controller/Driver Block Diagram 4 Display Data Memory 1FFH 3 2 1 0 3 1FEH 2 1 0 3 1F9H 2 1 0 3 1F8H 2 1 0 1E0H 32 10 8 Display Mode Register 4 Display Control Register 4 Port 3 Output Latch 10 8 Port Mode Register Group A 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 32 10 Timing Controller fLCD Multiplexer Selector Segment Driver Common Driver LCD Drive Voltage Control PD75312B, 75316B S31/BP7 S30/BP6 S24/BP0 S23 S0 COM3 COM2COM1COM0 V LC2 VLC1 VLC0 P31/ P30/ SYNC LCDCL 27 PD75312B, 75316B 5.9 BIT SEQUENTIAL BUFFER ..... 16 BITS The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing data with long bit lengths bit-wise. Fig. 5-8 Bit Sequential Buffer Format Address Bit Symbol FC3H 3 2 1 BSB3 0 3 2 FC2H 1 BSB2 0 3 2 FC1H 1 0 3 2 1 FC0H 0 BSB0 BSB1 L Register L = F L=CL=B INCS L L=8L=7 DECS L L=4 L=3 L=0 Remark In "pmem.@L" addressing, the specified bit corresponding to the L register is moved. 28 PD75312B, 75316B 6. INTERRUPT FUNCTION The PD75316B has six interrupt sources which enable multiple interrupt by software control. It also has two test sources, of which the INT2 has two edge detection testable inputs. Table 6-1. Types of Interrupt Sources Interrupt sources Internal/external Interrupt priorityNote 1 Vectored interrupt request signal (vector table address) INTBT (standard interval signal from basic interval timer) (both rising and falling edge detection are valid.) (Rising or falling detection edge is selected.) Internal 1 VRQ1 (0002H) INT4 External INT0 INT1 External External Internal 2 3 4 VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) INTCSI (serial data transfer end signal) INTT0 (match signal between the count register and modulo register of programmable timer/counter) Internal 5 VRQ5 (000AH) INT2Note 2 (rising edge detection of input to INT2 pin or falling edge detection of input to KR0-KR7) INTWNote 2 (signal from clock timer) External Testable input signal (IRQ2 and IRWQ are set.) Internal Notes 1. 2. Interrupt priority is serviced according to the order of priority, when several interrupt requests are generated simultaneously. Test source. They are affected by the interrupt enable flag in the same way as the interrupt source, but no vectored interrupt is generated. The PD75316B interrupt control circuit has the following functions: * Hardware control vectored interrupt function that can control interrupt acknowledgement by interrupt flag (IExxx) and interrupt master enable flag (IME). * Interrupt start address can be set. * Interrupt request flag (IRQxxx) test function (interrupt generation confirmation by software possible). * Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible). 29 INT2 /P12 KR0/P60 KR7/P73 Rising Edge Detector Selector 30 Fig.6-1 Interrupt Control Circuit Block Diagram Internal Bus 2 IM2 1 IM1 3 IM0 Interrupt Enable Flag (IEXXX) IME IST0 INT BT INT4 /P00 INT0 /P10 INT1 /P11 * Both Edges Detector Edge Detector Edge Detector Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQW IRQ2 Standby Release Signal Priority Control Circuit Vector Table Address Generator VRQn INTCSI INTT0 INTW PD75312B, 75316B Falling Edge Detector IM2 * Noise Eliminator PD75312B, 75316B 7. STANDBY FUNCTION To reduce the power consumption during program wait, the PD75316B has two standby modes: STOP mode and HALT mode. Table 7-1 Operation Status at Standby Mode STOP Mode Setting instruction STOP instruction HALT Mode HALT instruction Main system clock or subsystem clock settable Only CPU clock stopped (oscillation continued) Operable (IRQBT set at reference time intervals)* System clock at setting Only main system clock settable Clock generator Only main system clock oscillation stopped Basic interval timer Stopped Serial interface Operation Status Operable only when external SCK input selected as serial clock Operable only when TI0 pin input specified as count clock Operable only when fXT selected as count clock Operable only when fXT selected as LCDCL INT1, 2, 4: Operable Only INT0 inoperable Stopped Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input Operable* Timer/event counter Operable* Watch timer Operable LCD controller Operable External interrupt CPU Release signal Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input * Cannot be operable during main system clock stop. 31 PD75312B, 75316B 8. RESET FUNCTION The PD75316B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input Wait (31.3 ms/4.19 MHz) RESET Input Operating Mode or Standby Mode HALT Mode Operating Mode Internal Reset Operation Table 8-1 Status of Each Hardware after Resetting (1/3) Hardware RESET Input in Standby Mode Low-order 6 bits of program memory address 0000H are set in PC13 to 8 and the contents of address 0001H are set in PC7 to 0. Held 0 0 Bit 7 of program memory address 0000H is set in MBE. Undefined Held* Held 0 RESET Input During Operation Program counter (PC) Same as the left Carry flag (CY) Skip flag (SK0 to 2) PSW Interrupt status flag (IST0) Undefined 0 0 Bank enable flag (MBE) Same as the left Stack pointer (SP) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS) Undefined Undefined Undefined 0 * Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input. 32 PD75312B, 75316B Table 8-1 Status of Each Hardware after Resetting (2/3) Hardware RESET Input in Standby Mode Undefined 0 0 FFH 0 0, 0 0 Held 0 0 Held 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 RESET Input During Operation Undefined 0 0 FFH 0 0, 0 0 Undefined 0 0 Undefined 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 Basic interval timer Counter (BT) Mode register (BTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter Watch timer Mode register (WM) Shift register (SIO) Operating mode register (CSIM) Serial interface SBI control register (SBIC) Slave address register (SVA) Processor clock control register (PCC) Clock generator, clock output circuit System clock control register (SCC) Clock output mode register (CLOM) Display mode register (LCDM) LCD controller Display control register (LCDC) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt function Interrupt master enable flag (IME) INT0, 1, 2 mode registers (IM0, 1, 2) 33 PD75312B, 75316B Table 8-1 Status of Each Hardware after Resetting (3/3) Hardware RESET Input in Standby Mode OFF Clear (0) 0 RESET Input During Operation OFF Clear (0) 0 Output buffer Output latch Digital port I/O mode register (PMGA, B) Pull-up resistor specification register (POGA) Bit sequential buffer (BSB0 to 3) 0 0 Held Undefined 34 PD75312B, 75316B 9 INSTRUCTION SET (1) Operand identifier and description method The operand is described in the operand field of each instruction in accordance with the description method for the operand identifier of the instruction. For details refer to RA75X Assembler Package User's Manual Language Volume (EEU-1363). When there are multiple elements in the description method, one of the elements is selected. Uppercase letters and symbols (+,-) are keywords and should be described without change as shown. For immediate data, a suitable value or label is described. Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (see the PD75308 User's Manual (IEM-1263) for details). However, there are restrictions on the labels for which fmem and pmem can be used. Identifier reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem* bit fmem pmem addr caddr faddr taddr PORTn IExxx MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL Description 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label PD75312B PD75316B 0000H to 2F7FH immediate data or label 0000H to 3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT 0 to PORT 7 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB2, MB3, MB15 * For mem, only even addresses can be entered in the case of 8-bit data processing. 35 PD75312B, 75316B (2) Operation description legend A : A register; 4-bit accumulator B : B register; C D E H L X XA BC DE HL PC SP CY PSW MBE PORTn IME IExxx MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : C register; D register; E register; H register; L register; X register; Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Portn (n = 0 to 7) Interrupt master enable flag Interrupt enable flag Memory bank selection register Processor clock control register : Address, bit delimiter : Contents addressed by xx : Hexadecimal data 36 PD75312B, 75316B (3) Description of addressing area field symbols *1 *2 MB = MBE * MBS (MBS = 0 to 3, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0 to 3, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH *3 Data Memory Addressing *4 *5 *6 *7 PD75312B PD75316B addr = 0000H to 2F7FH addr = 0000H to 3F7FH addr = (Current PC) -15 to (Current PC) -1, (Current PC) +2 to (Current PC) + 16 caddr = 0000H to 0FFFH (PC13 = 0, PC12 = 0)or PD75312B 1000H to 1FFFH (PC13 = 0, PC12 = 1) or 2000H to 2F7FH (PC13 = 1, PC12 = 0) Program Memory Addressing *8 caddr = 0000H to 0FFFH (PC13 = 0, PC12 = 0) or PD75316B 1000H to 1FFFH (PC13 = 0, PC12 = 1) or 2000H to 2FFFH (PC13 = 1, PC12 = 0) or 3000H to 3F7FH (PC13 = 1, PC12 = 1) *9 *10 faddr = 0000H to 07FFH taddr = 0020H to 007FH Remarks 1. 2. 3. 4. MB indicates the accessible memory bank. For *2, MB = 0 without regard to MBE and MBS. For *4 and *5, MB = 15 without regard to MBE and MBS. *6 to *10 indicate the addressable area. (4) Explanation of machine cycle field S shows the number of machine cycles required when skip is performed by an instruction with skip. The value of S changes as follows: * No skip ....................................................................................................................................................................... S = 0 * When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1 * When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction) ............................. S = 2 Caution One machine cycle is required to skip a GETI instruction. One machine cycle is equivalent to one cycle (= tCY) of the CPU clock . Three times can be selected by PCC setting. 37 PD75312B, 75316B Mnemonic Machine Cycles Note 1 Bytes Operand Operation A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM A A + n4 A A + (HL) A, CY A + (HL) + CY A A - (HL) A, CY A - (HL) - CY A A n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL) Addressing Area Skip Condition Stack A A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL MOV @HL, A @HL, XA A, mem Transfer XA, mem mem, A mem, XA A, reg XA, rp reg1, A rp1, XA A, @HL A, @rpa1 XA, @HL XCH A, mem XA, mem A,reg1 XA, rp Note 2 XA, @PCDE MOVT XA, @PCXA A, #n4 ADDS A, @HL ADDC SUBS Operation SUBC AND A, @HL A, @HL A, @HL A, #n4 A, @HL OR A, #n4 A, @HL XOR A, #n4 A, @HL 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1+S 1+S 1 1+S 1 2 1 2 1 2 1 Stack A Stack B *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *2 *1 *3 *3 carry *1 *1 *1 *1 borrow carry *1 *1 *1 Notes 1. Instruction Group 2. Table reference 38 PD75312B, 75316B Mnemonic RORC NOT A A reg Machine Cycles Note 1 Bytes Operand Operation CY A0, A3 CY, An-1 An AA reg reg + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear Addressing Area Skip Condition Note 2 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S reg = 0 *1 *3 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 *1 (HL) = n4 A = (HL) A = reg Note 3 INCS @HL mem DECS Comparison reg reg, #n4 SKE @HL, #n4 A, @HL A, reg SET1 Note 4 CLR1 SKT NOT1 CY CY CY CY mem.bit CY = 1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 SET1 fmem.bit pmem.@L @H + mem.bit mem.bit CLR1 Memory bit manipulation fmem.bit pmem.@L @H + mem.bit mem.bit SKT fmem.bit pmem.@L @H + mem.bit mem.bit (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 SKF fmem.bit pmem.@L @H + mem.bit fmem.bit (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 SKTCLR pmem.@L @H + mem.bit Notes 1. Instruction Group 2. Accumulator operation 3. Increment/decrement 4. Carry flag manipulation 39 PD75312B, 75316B Machine Cycles Note 1 Bytes Mnemonic Operand Operation Addressing Area *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip Condition CY, fmem.bit Memory bit manipulation AND1 CY, pmem.@L 2 2 2 2 2 2 2 2 2 2 2 CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY V (fmem.bit) CY CY V (pmem7-2 + L3-2.bit (L1-0)) CY CY V (H + mem3-0.bit) CY CY V (fmem.bit) CY CY V (pmem7-2 + L3-2.bit (L1-0)) CY CY V (H + mem3-0.bit) PC13-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) PC13-0 addr PC13-0 addr PC13-0 PC13, 12 + caddr11-0 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, PC13, PC12 PC13-0 addr, SP SP - 4 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, 0, PC13, PC12 PC13-0 00, faddr, SP SP - 4 MBE, PC13, PC12 (SP + 1)3, 1, 0 PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 MBE, PC13, PC12 (SP + 1)3, 1, 0 PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4, then skip unconditionally PC13, PC12 (SP + 1)1, 0 PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) 0, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), SP SP + 2 IME 1 IE x x x 1 IME 0 IE x x x 0 CY, @H + mem.bit 2 CY, fmem.bit OR1 CY, pmem.@L 2 2 CY, @H + mem.bit 2 CY, fmem.bit XOR1 CY, pmem.@L 2 2 CY, @H + mem.bit 2 addr Branch BR !addr $addr BRCB !caddr -- -- 3 1 2 3 2 2 CALL !addr 3 3 CALLF Subroutine stack control !faddr 2 2 RET 1 3 RETS 1 3+S RETI 1 rp 3 1 2 1 2 2 1 2 1 2 2 2 2 2 PUSH BS rp POP BS Note 2 EI IE x x x 2 2 DI IE x x x 2 Notes 1. Instruction Group 2. Interrupt control 40 V V V *6 *6 *7 *8 *6 *9 Unconditional PD75312B, 75316B Machine Cycles Note 1 Bytes Mnemonic Operand Operation Addressing Area Skip Condition Input/output IN A, PORTn XA, PORTn 2 2 2 2 2 2 1 2 2 2 2 2 2 1 2 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation MBS n (n = 0 to 3, 15) (n = 0-7) (n = 4, 6) (n = 2-7) (n =4, 6) OUT HALT STOP NOP SEL PORTn, A PORTn, XA Note 2 MBn 2 Special * TBR Instruction PC13-0 (taddr) 5-0 + (taddr + 1) ----------------------------------------------------------------------* TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 GETI taddr 1 3 (SP - 3) MBE, 0, PC13, PC12 PC13-0 (taddr) 5-0 (taddr + 1) SP SP - 4 ----------------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) *10 ----------------------------- ----------------------------Conforms to referenced instruction. Caution: At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance. Notes 1. Instruction Group 2. CPU control Remark The TBR and TCALL instructions are assembler pseudo instructions for GETI instruction table definition. 41 PD75312B, 75316B 10. MASK OPTION SELECTION The following mask options are available at the pins: Pin Function P40 to P43, P50 to P53 VLC0 to VLC2, BIAS Mask Option * Pull-up resistor (specifiable bit-wise) * No pull-up resistor (specifiable bit-wise) * LCD drive power supply split resistor (specified in units of 4) * No LCD drive power supply split resistor (specified in units of 4) 42 PD75312B, 75316B 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 C) PARAMETER Supply voltage SYMBOL VDD VI1 TEST CONDITIONS RATING -0.3 to +7.0 UNIT V V V V V mA mA mA mA mA mA mA mA C C Except ports 4, 5 On-chip pull-up resistor Ports 4, 5 Open-drain -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +11 -0.3 to VDD +0.3 Input voltage VI2 Output voltage Output current, high VO IOH Per pin All output pins Per pin Output current, low -15 -30 Peak value Effective value Peak value 30 15 100 60 100 60 -40 to +85 -65 to +150 IOL* Total of ports 0, 2, 3, 5 Effective value Peak value Effective value Total of ports 4, 6, 7 Operating temperature Storage temperature Topt Tstg * Calculate the effective value with the formula [Effective value] = [Peak value] x duty. If even one parameter exceeds the absolute maximum rating, even momentarily, the quality of the product may be impaired. The absolute maximum rating is a rated threshold value at which the product can be physically damaged. Be sure to use the product within the absolute maximum ratings. Caution: CAPACITANCE (Ta = 25 C, VDD = 0 V) PARAMETER Input capacitance Output capacitance Input /output capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pin returned to 0 V TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF 43 PD75312B, 75316B MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXX) *1 After VDD reaches the minimum value in the oscillation voltage range 1.0 VDD = 4.5 to 6.0 V C1 VDD X1 input frequency (fX) *1 1.0 C2 Oscillation stabilization time *2 4.19 TEST CONDITIONS MIN. 1.0 TYP. MAX. 5.0*3 UNIT MHz X1 X2 Ceramic resonator C1 VDD C2 Oscillation stabilization time *2 4 ms X1 Crystal resonator X2 Oscillator frequency (fXX) *1 5.0*3 10 30 MHz ms ms X1 External clock X2 5.0*3 MHz PD74HCU04 X1 input high and low level widths (tXH, tXL) 100 500 ns * 1. For the oscillator frequency and the X1 input frequency, only the characteristics of the oscillation circuit are shown. For the instruction execution time, refer to the AC characteristics. 2. Time required for oscillation to become stabilized after VDD application or STOP mode release. When the oscillator frequency is 4.19 MHz < fXX 5.0 MHz, do not select PPC = 0011 as instruction execution time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 s, with the result that specified MIN. value 0.95 s cannot be observed. 3. SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXT) TEST CONDITIONS MIN. 32 TYP. 32.768 MAX. 35 UNIT kHz XT1 Crystal resonator XT2 R VDD = 4.5 to 6.0 V Oscillation stabilization time* 1.0 2 s C3 C4 VDD 10 s X1 External clock X2 XT1 input frequency (fXT) 32 100 kHz Open XT1 input high and low level widths (tXTH, tXTL) 5 15 s * Time required for oscillation to become stabilized after VDD application. 44 PD75312B, 75316B Caution: When the main system clock oscillator or subsystem clock oscillator is used, the shaded area in the figures should be wired as follows to prevent influence from the wiring capacitance, etc. * Wiring should be as short as possible. * Do not cross signal lines. * Do not place the circuit close to a line in which varying high current flows. * The connecting point of oscillator capacitor should always be the same potential as VDD. Do not connect it to the power supply pattern in which high current flows. * Do not fetch a signal from the oscillator. When the subsystem clock is used, special care is needed for the wiring. The subsystem clock oscillator is designed to be low-amplification circuit for low current consumption, thus mulfunction due to noise occurs more often than with the main system clock oscillator. 45 PD75312B, 75316B RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = -40 to +85 C) Recommended constants Manufacture Product Name CSB x x x x J CSAx. x x xMK040 CSA x. x x MG040 CST x. x x MG040 CSA x. x x MG CST x. x x MGW 2.450 to 5.000 Internal Internal 1.800 to 2.440 Internal 30 Internal 30 - Frequency (MHz) C1 (pF) MURATA 1.000 to 1.250 1.251 to 1.799 100 100 C2 (pF) R (k) 5.6 Oscillator voltage range (V) MIN. MAX. 2.0 6.0 MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = -40 to +85 C) Recommended constants Oscillator voltage range (V) Manufacture Product Name Frequency (MHz) C1 (pF) KYOCERA KBR-1000Y 1.00 KBR-1000F 100 KBR-2.0MS 2.00 PBRC 2.00A KBR-4.0MSA 33 PBRC 4.00A 4.00 KBR-4.0MKS Internal KBR-4.0MWS KBR-5.0MSA 33 PBRC 5.00A 6.00 KBR-5.0MKS Internal KBR-5.0MWS Internal 33 Internal 2.0 6.0 33 100 C2 (pF) MIN. MAX. 46 PD75312B, 75316B MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = -40 to +85 C) Recommended constants Oscillator voltage range (V) Manufacture Product Name Frequency (MHz) C1 (pF) TOKOU CRHF 2.50 CRHF 3.00 CRHF 4.00 CRHF 5.00 2.5 3.0 30 4.0 5.0 30 2.0 6.0 C2 (pF) MIN. MAX. SUBSYSTEM CLOCK: CRYSTAL RESONATOR (Ta = -15 to +60 C) Recommended constants Manufacture Product Name Frequency (MHz) C3 (pF) KYOCERA KF-38G 32.768 18 C4 (pF) 33 R (k) 220 Oscillator voltage range (V) MIN. 2.0 MAX. 6.0 Caution: Make the fine-adjustment of crystal resonator frequency with external capacitor C1 or C3. 47 PD75312B, 75316B DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V ) (1/2) PARAMETER SYMBOL VIH1 TEST CONDITIONS Ports 2 and 3 Ports 0, 1, 6, 7, RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7, BIAS VDD = 4.5 to 6.0 V IOH = -1mA IOH = -100 A VDD = 4.5 to 6.0 V IOH = -100 A IOH = -30 A Ports 3, 4, 5 VDD = 4.5 to 6.0 V IOL = 15 mA VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A SB0, 1 Open-drain pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A MIN. 0.7 VDD 0.8 VDD TYP. MAX. VDD VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V V Input voltage, high VIH2 VIH3 VIH4 VIL1 On-chip pull-up resistor 0.7 VDD Open-drain 0.7 VDD VDD -0.5 0 0 0 Input voltage, low VIL2 VIL3 VOH1 Output voltage, high VDD -1.0 VDD -0.5 V V V0H2 BP0 to BP7 (with 2 IOH outputs) VDD -2.0 V VDD -1.0 V 0.5 2.0 V VOL1 Output voltage, low Ports 0, 2, 3, 4, 5, 6 and 7 0.4 V V V 0.5 0.2 VDD VOL2 BP0 to BP7 (with 2 IOL outputs) 1.0 V 1.0 3 20 V ILIH1 VIN = VDD Input leakage current, high ILIH2 Other than below A A X1, X2, XT1 Ports 4 and 5 (when open -drain) Other than below ILIH3 VIN = 10 V 20 A Input leakage current, low ILIL1 VIN = 0 V ILIL2 -3 -20 A A X1, X2, XT1 48 PD75312B, 75316B DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V ) (2/2) PARAMETER SYMBOL ILOH1 TEST CONDITIONS VOUT = VDD Other than below Ports 4 and 5 (when opendrain) MIN. TYP. MAX. 3 UNIT A Output leakage current, high ILOH2 Output leakage current, low VOUT = 10 V 20 A ILOL VOUT = 0 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% -3 A RL1 On-chip pull-up resistor RL2 Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V 15 40 80 k 30 15 40 200 k k 70 Ports 4, 5 VOUT = VDD -2.0 V 15 2.0 60 40 70 VDD k V k LCD drive voltage LCD split resistor LCD output voltage deviation*1 (common) LCD output voltage deviation*1 (segment) VLCD RLCD 100 150 VODC IO = 5 A VODS IO = 1A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD 0 0.2 V 0 0.2 V IDD1 4.19 MHz*3 crystal oscillation C1=C2= 22 pF VDD = 5 V 10%*4 VDD = 3 V 10%*5 VDD = 5V 10% VDD = 3V 10% 3.0 9 mA 0.4 1.2 mA 1 3 mA IDD2 Supply current *2 HALT mode 300 900 A IDD3 32 kHz *6 crystal oscillation IDD4 VDD = 3 V 10% HALT mode VDD = 3V 10% 20 60 A 7 21 A VDD = 5 V10% XT1 = 0 V STOP mode 1 0.5 25 15 A A A IDD5 VDD = 3V 10% Ta = 25C 0.5 5 49 PD75312B, 75316B * 1. 2. 3. 4. 5. 6. The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n = 0, 1, 2) and output voltage. Current flowing in the internal pull-up resistor and LCD split resistor are not included. Includes the case when the subsystem clock is oscillated. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. When the PCC is set to 0000 and operated in low-speed mode. When operated by the subsystem clock with the system clock control register (SCC) set to 1001 and the main system clock oscillation stopped. 50 PD75312B, 75316B AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V ) PARAMETER SYMBOL TEST CONDITIONS Operation with main system clock VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 TYP. MAX. 64 64 UNIT s s s MHZ kHz CPU clock cycle time (minimum instruction execution time = one machine cycle)*1 tCY Operation with subsystem clock VDD = 4.5 to 6.0 V fTI 275 VDD = 4.5 to 6.0 V 0.48 1.8 INT0 *2 10 10 10 122 125 1 TI0 input frequency TI0 input high- and lowlevel widths tTIH, tTIL s s s s s s Interrupt input high- and low-level widths tINTH, INT1, 2, 4 tINTL KR0-7 RESET low-level width tRSL * 1. CPU clock () cycle time is determined by oscillation frequency of the connected resonator, system clock control register (SCC) and processor clock control register (PCC). Characteristics for supply voltage VDD vs. Cycle time tCY in main system clock operation is shown below. tCY 70 64 60 6 5 VS VDD (Main System Clock in Operation) 2. Cycle Time tCY [s] It becomes 2tCY or 128/fX by interrupt mode register (IM0) setting. Operation guarantee range 4 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 51 PD75312B, 75316B SERIAL TRANSFER OPERATION 2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V ) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 SCK high- and low-level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL1 tKH1 tSIK1 tKSI1 tKSO1 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 150 400 250 1000 ns ns ns ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns * RL and CL are SO output line load resistance and load capacitance, respectively. 2-wire and 3-wire serial I/O mode (SCK...External clock input): (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY2 3200 SCK high- and low-level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 tSIK2 tKSI2 tKSO2 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 1000 ns ns ns ns ns ns ns TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns * RL and CL are SO output line load resistance and load capacitance, respectively. 52 PD75312B, 75316B SBI mode (SCK...Internal clock output (master)): (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY3 TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 1600 3800 TYP. MAX. UNIT ns ns ns ns ns ns SCK high- and low-level widths SB0 and SB1 setup time (to SCK) tKL3 tKH3 tSIK3 tKSI3 tKSO3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 250 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH tKCY3 tKCY3 tKCY3 tKCY3 * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. SBI mode (SCK...External clock input (slave)): (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY4 3200 SCK high- and low-level widths SB0 and SB1 setup time (to SCK) TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns ns ns ns ns ns tKL4 tKH4 tSIK4 tKSI4 tKSO4 VDD = 4.5 to 6.0 V 400 1600 100 tKCY4/2 SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 300 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH tKCY4 tKCY4 tKCY4 tKCY4 * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. 53 PD75312B, 75316B DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V ) (1/2) PARAMETER SYMBOL VIH1 TEST CONDITIONS Ports 2 and 3 Ports 0, 1, 6, 7, RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7, BIAS MIN. 0.8 VDD 0.8 VDD TYP. MAX. VDD VDD VDD 10 VDD 0.2 VDD 0.2 VDD 0.25 UNIT V V V V V V V V Input voltage, high VIH2 VIH3 VIH4 VIL1 On-chip pull-up resistor 0.8 VDD Open-drain 0.8 VDD VDD -0.3 0 0 0 Input voltage, low VIL2 VIL3 VOH1 Output voltage, high IOH = -100 A VDD -0.5 V VOH2 BP0 to BP7 (with 2 IOH outputs) IOH = -10 A VDD -0.4 V Ports 0, 2, 3, 4, 5, 6 and 7 VOL1 Output voltage, low SB0, 1 IOL = 400 A 0.5 V Open-drain pull-up resistor 1 k IOL = 10 A 0.2 VDD V VOL2 BP0 to BP7 (with 2 IOL outputs) 0.4 V ILIH1 VIN = VDD Input leakage current, high ILIH2 Other than below 3 20 A A X1, X2, XT1 Ports 4 and 5 (when open -drain) Other than below ILIH3 VIN = 10 V 20 A Input leakage current, low ILIL1 VIN = 0 V ILIL2 ILOH1 -3 -20 3 A A A X1, X2, XT1 VOUT = VDD Other than below Output leakage current, high ILOH2 VOUT = 10 V Ports 4 and 5 (when open -drain) 20 A Output leakage current, low ILOL VOUT = 0 V -3 A 54 PD75312B, 75316B DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V ) (2/2) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT RL1 On-chip pull-up resistor RL2 Ports 0, 1, 2, 3, 6 and 7 (except P00) VIN = 0 V VDD = 2.5 V 10% 50 600 k Ports 4, 5 VOUT = VDD -1.0 V VDD = 2.5 V 10% 15 40 70 k LCD drive voltage LCD split resistor LCD output voltage deviation*1 (common) LCD output voltage deviation*1 (segment) VLCD RLCD 2.0 60 100 VDD 150 V k VODC IO = 5 A VODS IO = 1A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.0 V VLCD VDD VDD = 3 V 10%*4 0 0.2 V 0 0.2 V 0.4 1.2 mA IDD1 4.19 MHz*3 crystal oscillation C1=C2=22 pF Low-speed mode IDD2 VDD = 2.5 V 10%*4 VDD = 3V 10% VDD = 2.5 V 10% 0.3 0.9 mA 300 900 A HALT mode 200 600 A A A A Supply current *2 IDD3 32 kHz *5 crystal oscillation IDD4 VDD = 3 V 10% VDD = 2.5 V 10% VDD = 3V 10% VDD = 2.5 V 10% 20 15 7 60 45 21 HALT mode 4 12 A A A A A VDD = 3V 10% IDD5 XT1 = 0 V STOP mode VDD = 2.5 V 10% 0.5 Ta = 25C 0.5 0.4 Ta = 25C 0.4 15 5 15 5 55 PD75312B, 75316B * 1. 2. 3. 4. 5. The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n = 0, 1, 2) and output voltage. Current flowing in the on-chip pull-up resistor and LCD split resistor are not included. Includes the case when the subsystem clock is oscillated. When the PCC is set to 0000 and operated in low-speed mode. When operated by the subsystem clock with the system clock control register (SCC) set to 1001 and the main system clock stopped. 56 PD75312B, 75316B AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.0 to 6.0 V ) PARAMETER SYMBOL TEST CONDITIONS VDD = 2.7 to 6.0 V CPU clock cycle time (minimum instruction execution time = one machine cycle)*1 tCY Operation with main system clock VDD = 2.0 to 6.0 V Ta = -4.0 to +6.0 V VDD = 2.2 to 6.0 V MIN. 3.8 5 3.4 114 0 122 TYP. MAX. 64 64 64 125 275 UNIT s s s s kHz Operation with subsystem clock TI0 input frequency TI0 input high- and lowlevel widths fTI tTIH, 1.8 tTIL INT0 *2 10 10 10 s s s s s Interrupt input high- and low-level widths tINTH, INT1, 2, 4 tINTL KR0-7 RESET low-level width tRSL * 1. CPU clock () cycle time is determined by oscillation frequency of the connected resonator, system clock control register (SCC) and processor clock control register (PCC). Characteristics for supply voltage VDD vs. Cycle tCY 70 64 60 6 5 Operation guarantee range VS VDD (Main System Clock in Operation) time tCY in main system clock operation is shown below. 2. It becomes 2tCY or 128/fX by interrupt mode register (IM0) setting. 4 Cycle Time tCY [s] 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 57 PD75312B, 75316B SERIAL TRANSFER OPERATION 2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (Ta = -40 to +85 C , VDD = 2.0 to 6.0 V ) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 SCK high- and low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL1 tKH1 tSIK1 tKSI1 tKSO1 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 250 400 250 1000 ns ns ns ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns * RL and CL are SO output line load resistance and load capacitance, respectively. 2-wire and 3-wire serial I/O mode (SCK...External clock input): (Ta = -40 to +85 C , VDD = 2.0 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY2 3200 SCK high- and low-level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 tSIK2 tKSI2 tKSO2 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 1000 ns ns ns ns ns ns ns TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns * RL and CL are SO output line load resistance and load capacitance, respectively. 58 PD75312B, 75316B SBI mode (SCK...Internal clock output (master)): (Ta = -40 to +85 C , VDD = 2.0 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY3 TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 1600 3800 TYP. MAX. UNIT ns ns ns ns ns ns SCK high- and low-level widths SB0 and SB1 setup time (to SCK) tKL3 tKH3 tSIK3 tKSI3 tKSO3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 250 tKCY3/2 SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 250 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH tKCY3 tKCY3 tKCY3 tKCY3 * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. SBI mode (SCK...External clock input (slave)): (Ta = -40 to +85 C , VDD = 2.0 to 6.0 V ) PARAMETER SCK cycle time SYMBOL tKCY4 3200 SCK high- and low-level widths SB0 and SB1 setup time (to SCK) TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns ns ns ns ns ns tKL4 tKH4 tSIK4 tKSI4 tKSO4 VDD = 4.5 to 6.0 V 400 1600 100 tKCY4/2 SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 300 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH tKCY4 tKCY4 tKCY4 tKCY4 * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. 59 PD75312B, 75316B AC Timing Test Points (except X1 and XT1 input) 0.8 VDD 0.2 VDD Test points 0.8 VDD 0.2 VDD Clock Timing 1/fX tXL tXH V DD -0.5 V 0.4 V X1 input 1/fXT tXTL tXTH V DD -0.5 V 0.4 V XT1 input TI0 Timing 1/fTI tTIL tTIH TI0 60 PD75312B, 75316B Serial Transfer Timing 3-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI Input data tKSO1 SO Output data 2-wire serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SBO, 1 tKSO2 61 PD75312B, 75316B Serial Transfer Timing Bus release signal transfer: tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer: tKCY3, 4 tKL3, 4 tKH3, 4 K SCK tKSB tSBK tSIK3, 4 tKSI3, 4 0, 1 SB0, 1 tKSO3, 4 Interrupt Input Timing tINTL tINTH INT0, 2, 4 KR0-7 RESET Input Timing tRSL RESET 62 PD75312B, 75316B DATA RETENTION CHARACTERISTICS IN DATA MEMORY STOP MODE AND LOW SUPPLY VOLTAGE (Ta = -40 to +85 C) PARAMETER Data retention supply voltage Data retention supply current *1 Release signal set time Oscillation stabilization wait time *2 SYMBOL VDDDR IDDDR tSREL Release by RESET tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fX TEST CONDITIONS MIN. 2.0 0.3 TYP. MAX. 6.0 15 UNIT V A s ms * 1. 2. 3. Current to the on-chip pull-up resistor is not included. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (see below). Wait Time BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 (Values at fX = 4.19 MHz in parentheses) 0 1 1 1 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution tSREL RESET tWAIT 63 PD75312B, 75316B Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT tSREL 64 PD75312B, 75316B 12. CHARACTERISTIC CURVES (For Reference Only) IDD vs VDD (Ceramic Oscillation: 4.19 MHz) (Ta = 25 C) 5000 High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 Main system clock HALT mode 1000 500 Power supply current IDD (A) 100 Main system clock STOP mode + subsystem clock operating mode Main system clock STOP mode + 32 kHz oscillation only or subsystem clock HALT mode 50 10 5 X1 X2 XT1 XT2 Ceramic resonator CSA4.19 MG Crystal 32.768 kHz 330 k 30 pF 30 pF 22 pF 22 pF VDD VDD 1 0 1 2 3 5 4 Power supply voltage VDD (V) 6 7 65 PD75312B, 75316B IDD vs VDD (Ceramic Oscillation: 2.00 MHz) (Ta = 25 C) 5000 High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 Main system clock HALT mode 1000 500 Power supply current IDD (A) 100 Main system clock STOP mode + subsystem clock operating mode Main system clock STOP mode + 32 kHz oscillation only or subsystem clock HALT mode 50 10 5 X1 Ceramic resonator X2 XT1 XT2 CSA2.00 MG 040 Crystal 32.768 kHz 330 k 100 pF 100 pF 22 pF 22 pF VDD VDD 1 0 1 2 3 4 Power supply voltage VDD (V) 5 6 7 66 PD75312B, 75316B IOL vs VOL (Port 0, 2, 6, and 7) VDD = 5 V VDD = 6 V VDD = 4 V (Ta = 25C) 20 VDD = 3 V IOL (mA) 10 VDD = 2.0 V 0 0 1.0 2.0 VOL (V) 3.0 IOL vs VOL (Port 3, 4, and 5) VDD = 5 V VDD = 6 V VDD = 4 V (Ta = 25C) 20 VDD = 3 V IOL (mA) 10 VDD = 2.0 V 0 0 1.0 2.0 VOL (V) 3.0 67 PD75312B, 75316B IOH vs VOH VDD = 5 V VDD = 6 V VDD = 4 V (Ta = 25C) 10 VDD = 3 V IOH (mA) 5 VDD = 2.0 V 0 0 1.0 2.0 VDD-VOH (V) 3.0 68 PD75312B, 75316B 13. PACKAGE DRAWINGS 80 PIN PLASTIC QFP ( 14) A B 60 61 41 40 detail of lead end D C S 80 1 21 20 F G H IM J K P N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. M INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX. 55 Q 69 PD75312B, 75316B 80 PIN PLASTIC TQFP (FINE PITCH) ( A B 12) 60 61 41 40 detail of lead end C D S Q 80 21 1 20 F G H I M J K P N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4 70 M R PD75312B, 75316B 14. RECOMMENDED SOLDERING CONDITIONS The product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 14-1 Surface Mounting Type Soldering Conditions PD75312BGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm) PD75316BGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm) Soldering Method Soldering Conditions Package peak temperature: 235 C, Time: Within 30 s (at 210 C or higher), Count: Twice or less Package peak temperature: 215 C, Time: Within 40 s (at 200 C or higher), Count: Twice or less Wave soldering Soldering tank temperature: 260 C or less, Time: Within 10 s, Count: Once, Preheating temperature: 120 C MAX. (package surface temperature) Pin temperature: 300 C or less, Time: Within 3 s (per side of device) WS60-00-1 Partial heating Caution: Do not use several soldering methods in combination (except partial heating). 71 PD75312B, 75316B PD75312BGK-xxx-3B9 : 80-pin plastic QFP (12 x 12 mm) PD75316BGK-xxx-3B9 : 80-pin plastic QFP (12 x 12 mm) Recommended Condition Symbol Soldering Method Soldering Conditions Package peak temperature: 235 C, Time: Within 30 s (at 210 C or higher), Count: Twice or less, Exposure limit : Seven* days (after seven days, prebake at 125 C is required for 10 hours) Infrared reflow IR35-107-2 VPS Package peak temperature: 215 C, Time: Within 40 s (at 200 C or higher), Count: Twice or less, Exposure limit : Seven*days (after seven days, prebake at 125 C is required for 10 hours) VP15-107-2 Partial heating Pin temperature: 300 C or less, Time: Within 3 s (per side of device) * For the storage period after dry-pack decapsulation, storage conditions are max. 25 C, 65 % RH. Do not use several soldering methods in combination (except partial heating). Caution: 72 PD75312B, 75316B APPENDIX A. DIFFERENCES AMONG PD75308B SERIES PRODUCTS Name Item Supply voltage range ROM configuration Program memory (bytes) Data memory (x 4 bits) Instruction cycle CMOS input Input/ output port CMOS input/output 40 CMOS output N-ch open-drain input/output 8 8 Used with segment pin 10-V withstand voltage, pull-up resistor can be incorporated by mask option. 10-V withstand voltage, without pull-up resistor option Mask ROM 4096/6016/8064 512 0.95 s, 1.91 s, 15.3 s (main system clock:@ 4.19 MHz) 122 s (subsystem clock:@ 32.768 kHz) 8 Pull-up resistor can be incorporated by software: 23 16 12160 PD75304B/75306B/75308B PD75312B PD75316B 2.0 to 6.0 V PD75P316B PD75P316A EPROM/one-time PROM 16256 1024 * Common output: Static - 1/4 duty selected * Segment output: Max. 32 LCD controller/driver LCD drive split resistor can be incorporated by mask option. LCD drive voltage * 8-bit timer/event counter * 8-bit basic interval timer * Watch timer * NEC standard serial bus interface (SBI) * Clocked serial interface * External: 3 * Internal: 3 * External: 1 * Internal: 1 , 524 kHz, 262 kHz, 65.5 kHz (main system clock:@ 4.19 MHz) 2 kHz (main system clock:@ 4.19 MHz, or subsystem clock:@ 32.768 KHz) 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) 80-pin ceramic WQFN* 80-pin plastic QFP (14 x 20 mm) 80-pin ceramic WQFN No LCD drive split resistor 2.0 V to VDD Timer/counter Serial interface Vectored interrupts Test input Clock output (PCL) Buzzer output (BUZ) Package On-chip PROM product GF package : PD75P316A GC/GK package : PD75P316B PD75P316B * Under development 73 PD75312B, 75316B APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD75312B, 75316B. IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75308BGC-R Hardware EV-9200GC-80 EP-75308BGK-R EV-9200GK-80 PG-1500 PA-75P316BGC 75X series in-circuit emulator Emulation board for the IE-75000-R and the IE-75001-R Emulation probe for the PD75312BGC and the 75316BGC. 80-pin conversion socket EV-9200GC-80 is also provided. Emulation probe for the PD75312BGK and the 75316BGK. 80-pin conversion socket EV-9200GK-80 is also provided. PROM programmer PROM programmer adapter for the PD75P316BGC, connect to PG-1500. PROM programmer adapter for the PD75P316BGK, connect to PG-1500. Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3) IBM PC/ATTM (See "OS for IBM PC") PA-75P316BGK Software IE control program PG-1500 controler RA75X relocatable assembler * 1. 2. 3. Maintenance products Not incorporated in IE-75001-R. The task-swap function is provided with the Ver.5.00/5.00A and cannot be used with this software. OS for IBM PC The following OSs are supported for IBM PC OS PC DOSTM Version Ver.5.0.2 to Ver.6.1 J6.03/V Ver.3.30 to Ver.5.00A 5.0/V, J6.2/V J5.02/V MS-DOS IBM DOSTM Caution: Ver.5.0 or higher contains a task swap function; however, this function cannot be used by this software. 74 PD75312B, 75316B APPENDIX C. RELATED DOCUMENTATION List of Device-Related Documents Document Name User's Manual Application Note IEM-1245 75X Series Selection Guide IF-1027 Document No. IEM-1263 IEM-1239 List of Development Tool-Related Documents Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75308BGC-R User's Manual EP-75308BGK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language Document No. EEU-1416 EEU-1294 EEU-1406 EEU-1408 EEU-1335 EEU-1346 EEU-1363 EEU-1291 Others Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Device NEC Semiconductor Device Reliability and Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Micro Computer-Related Products Guide Other Manufacture Volume Document No. IEI-1213 IEI-1207 IEI-1209 -- -- MEI-1202 -- Remark The related documents listed above may change without prior notice. The most up-to-date documents should be used for design work. 75 PD75312B, 75316B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 76 PD75312B, 75316B The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of MicroSoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. |
Price & Availability of UPD75312B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |